Trabajo de Design Verification Engineer en Altran, Ontario - Canada

Design Verification Engineer

  • Sueldo ()

    No especificado

  • Lugar

    Ontario, Canada

  • Tipo de puesto

    Empleado de tiempo completo

Altran ranks as the undisputed global leader in Engineering and R&D services (ER&D). The company offers clients an unmatched value proposition to address their transformation and innovation needs. Altran works alongside its clients, from initial concept through industrialization, to invent the products and services of tomorrow. For over 35 years, the company has provided expertise in Automotive, Aeronautics, Space, Defense & Naval, Rail, Infra & Transport, Energy, Industrial & Consumer, Life Sciences, Communications, Semiconductor & Electronics, Software & Internet, Finance & Public Sector. The Aricent acquisition extends this leadership to semiconductor, digital experience and design innovation. Altran generated revenues of €2.9 billion in 2018, with some 47,000 employees in more than 30 countries.

Design Verification Engineer


Location: Hudson and Canada

Qualification/Experience/Skills Required:

-           Experience with following verification plans at full-chip (SoC) and block levels for complex designs

-           Writing UVM/OVM/VMM and System Verilog tests and coverage metrics for functional verification

-           Hands-on experience with large, automated, metric-driven simulation environments

-           Hands-on experience with debug tools, bug tracking and quality metrics and closure

-           Synopsys (VCS) and/or Cadence simulation/verification tools

-           5-10 years’ industry experience, BS EE or CE, MS preferred


Roles & Responsibilities:

-           Under close supervision, assist, research, design, develop and test electronic circuits, components and chips in CPU, telecommunication, networking, storage and graphic industry.

-           Day to day responsibilities for the position includes assisting in creating the verification plans, creating UVM test bench using latest verification platforms and tools based on HVL’s and System Verilog or VHDL, assist in developing efficient system/chip level test and regression environment and run simulation to achieve code and functional coverage goals.

-           Develop re-usable test environments, generating test cases and simulations to achieve code and functional goals, and performing verification design reviews.

-           Familiarity/experience with formal verification and/or assertions is a plus.